Mixers may be frequency translation devices. Mixers may allow the down and/or up conversion of signals from a high frequency (generally radio frequency (RF)) to a lower frequency (generally intermediate frequency (IF) or baseband) or vice versa. In communication systems, the RF may be the transmission frequency, which may be converted to an IF to allow improved selectivity (filtering) and an easier implementation of low noise and high gain amplification.
Referring to FIG. 1, a conventional double balanced FET ring is depicted. Ring double-balanced mixers may be described by treating the ring double-balanced mixer nonlinear components (diodes, BJTs or FETs) as switches, which are turned “on” and “off” by the local oscillator (LO). This approach assumes that the conductance waveform of the FET is a square wave, which is approximately true, as long as the LO power level is above a certain level and the LO's frequency is below a certain level, For instance, the LO power may be about 20 dBm (100 mW). The LO signal is configured to switch FETs 110 and 130 on and off in anti-phase with FETs 120 and 140. The RF signal and a 180 degree shifted version of the RF signal may be alternatively routed through to the IF port. The IF output is effectively the RE signal multiplied by a LO square wave of peak magnitude +/−1. Compared to diode mixers, FET mixers have better. P1 dB compression point performances. Also, compared to diode mixers, FET mixers have lower intermodulation distortion products and lower spurious signals due to higher linearity.
However, this approach, if implemented within a semiconductor device, requires a great deal of real estate on the die. Larger dies associated with the greater space demand increase the chances for imperfections within the die. In the traditional embodiment of FIG. 1, there are 6 interconnect lines coupling the RF+ signal, RF− signal, LO+ signal, LO− signal, RF− signal and RF+ signal to the system. Due to the physical separation of the 4 FETs these interconnect line lengths are longer than if the multiple FETs were located closer together or portions of the multiple FETs were removed. For instance, there are four total gates, four total sources, and four total drains. Each FET requires a conduit or coupling which introduces opportunities for losses and parasitic capacitances and discontinuities that may limit high frequency performance. As the frequency is increased the parasitic capacitance and distributed inductance from the interconnects introduce phase errors between the signals causing imperfect cancellation of spurious products from the balanced mixer configuration and higher loss. Also, larger MMIC die are more expensive as cost is approximately proportional to die size. Thus, smaller MMIC die size is more desirable because of reduced cost. Also, smaller MMIC die size is desirable due to improved high frequency performance.
Accordingly, there exists a need for a compact high linearity MMIC based mixer that reduces the die size. In addition, there is a need for a lower cost compact high linearity MMIC based mixer.